The present invention relates to a data transfer memory.
Philips Electronics has proposed an I2C (Inter-Integrated Circuit) bus, that is a two-wire serial bus. The I2C bus is used for operating a slave device in response to a transmission command issued by a master device. Operation of the I2C bus is described with reference to FIGS. 1 to 5.
As shown in FIG. 1, under a start condition, a serial clock line (SCL line) is at an H level while a serial data line (SDA line) shifts from an H level to an L level. All operations initiate from the start condition. Under a stop condition, the SCL line is at an H level while the SDA line shifts from an L level to an H level. The SCL line is a line into which a serial clock signal is input. The SDA line is a line used for data transfer.
A transmission command is issued by shifting the level of the SDA line when the SCL line is at an L level. The transmission command is a signal including eight consecutively transmitted bits. During a ninth clock cycle, a slave device receiving the command shifts the SDA line to an L level and outputs an acknowledgement indicating that it has received the command. In this manner, each command is issued and received in a unit of nine clock cycles.
FIG. 2 shows a byte write sequence in which data is written to a slave device in byte units by a master device. First, the master device transmits a start condition (START). The master device then transmits a slave address in seven clock cycles to select one of a plurality of slave devices for writing data. The master device further transmits an L level write command code (WRITE) during the eighth clock cycle. The selected slave device outputs an acknowledgement (ACK) when recognizing that it has been selected.
Upon receiving the acknowledgement, the master device transmits an 8-bit write address (word address) to the slave device. The slave device, recognizing the write address, outputs an acknowledgement (ACK). Upon receiving this acknowledgement, the master device further transmits 8-bit write data. When recognizing the write data, the slave device outputs an acknowledgement. Upon receiving the last acknowledgement, the master device transmits a stop condition (STOP). Upon recognizing the stop condition, the slave device starts writing the data.
FIG. 3 shows a current address read sequence in which a master device reads data in byte units from a slave device. First, the master device transmits a start condition (START). Subsequently, the master device transmits a slave address in seven clock cycles to select one of a plurality of slave devices from which data is to be read. The master device then transmits an H level command code (READ) during the eighth clock cycle. The slave device transmits an acknowledgement when recognizing that it has been selected.
After outputting the acknowledgement, the slave device outputs 8 bits of read data at the current address held by the slave device. Thereafter, the master device transmits a stop condition (STOP) without outputting an acknowledgement. This ends the-read operation of the slave device.
FIG. 4 shows a page write sequence in which data is written from a master device to a slave device in page units. First, the master device transmits a start condition. Then, the master device transmits a slave address in seven clock cycles to select one of a plurality of slave devices for writing data. The master device then transmits an L level write command code during the eighth clock cycle. The selected slave device outputs an acknowledgement when recognizing that it has been selected.
Upon receiving this acknowledgement, the master device outputs an 8-bit write address to the slave device. When recognizing the write address, the slave device outputs an acknowledgement. Upon receipt of this acknowledgement, the master device further transmits 8-bit write data (1). The slave device, recognizing the write data, outputs an acknowledgement. The master device then transmits 8-bit write data (2) corresponding to the next word address, and the slave device outputs an acknowledgement. Subsequently, the transmission of 8-bit write data from the master device and the output of an acknowledgement from the slave device are repeated to transmit a maximum page size of write data to the slave device. When the master device finally transmits a stop condition, the slave device starts writing the page size of data.
FIG. 5 shows a sequential read sequence in which a master device reads a plurality of data bytes from a slave device. First, the master device transmits a start condition. Subsequently, the master device transmits a slave address in seven clock cycles to select one of a plurality of slave devices from which data is to be read. The master device then transmits an H level read command code during the eighth clock cycle. The selected slave device outputs an acknowledgement when recognizing that it has been selected.
After outputting the acknowledgement, the slave device outputs 8-bit read data at the current address that it is holding. Subsequently, when the master device outputs an acknowledgement, the slave device outputs 8-bit read data for the next word address and the master device outputs an acknowledgement. Afterwards, the output of 8-bit read data from the slave device and the transmission of an acknowledgement from the master device are repeated continuously. When a memory address counter of the slave device reaches the last word address, the memory address counter rolls over to the top memory address. Finally, the master device transmits a stop condition without transmitting an acknowledgement. This terminates the sequential read operation of the plurality of data bytes from the slave device.
In recent years, the application fields for modules incorporating a plurality of electronic components have widened. FIG. 6 is a block diagram showing a conventional CCD camera module 50. The module 50 includes a charge coupled device (CCD) 10, an analog-digital (A/D) converter circuit 11 for converting an analog image signal output from the CCD 10 into a digital signal, and a digital signal processor (DSP) 12 for processing a digital image signal output from the A/D converter circuit 11. The DSP 12 is connected to a CPU 13 and a data memory 14 via an I2C bus 15. The data memory 14 stores a DSP control program and camera adjustment data (including, for example, white balance properties of the CCD 10 and instrumental error correction data for the mechanical shutter).
In response to power activation or an operation start switch signal from the CCD 10, the CPU 13 operates as a master device. The CPU 13 reads out the DSP control program and camera adjustment data (e.g., white balance properties) from the data memory 14 functioning as a slave device, via the I2C bus 15. Subsequently, the CPU 13, operating as the master device, writes the DSP control program and the camera adjustment data in the DSP 12 functioning as the slave device, via the I2C bus 15. The DSP 12 thus implements predetermined image data processing or camera adjustment (e.g., white balance correction or instrumental error correction for the mechanical shutter).
FIG. 7 is a block diagram showing the data memory 14 functioning as an I2C bus applicable slave device. An SCL terminal is an input terminal for receiving a serial clock signal and is connected to an input buffer 20. The SCL terminal performs signal processing at the rising and falling edges of the serial clock signal. An SDA terminal, which is used to perform bidirectional serial data transfer, is connected to an I/O buffer 21 including an input terminal and an open-drain output terminal. A condition-acknowledgement detection circuit 22 receives an output signal from the input buffer 20 and the I/O buffer 21 to detect a start or stop condition or an acknowledgement (ACK). A serial control circuit 23 receives a start/stop condition detection signal and an acknowledgement (ACK) detection signal, which are output from the condition-acknowledgement detection circuit 22, and an output signal from the I/O buffer 21. In accordance with the received signals, the serial control circuit 23 performs control to cause the I/O buffer 21 to output an acknowledgement, to write data in a nonvolatile memory 24, and to read data from the nonvolatile memory 24. When data is read from the nonvolatile memory 24, the serial control circuit 23 causes the I/O buffer 21 to output the read data.
A master device such as the CPU 13 is necessary in order to transfer data stored in the data memory 14 which functions only as a slave device. Therefore, with the data memory 14 of the prior art, the number of components configuring the module 50 cannot be decreased.